1. Field of the Invention
This invention relates to realization of a filter for high speed signal processing in a communication system and, more particularly, to a parallel filter realization suitable for implementation in a field programmable gate array for software defined radios.
2. Brief Description of Related Developments
Communication systems are widely used in many situations including communication between persons, as in cellular telephony, and between various forms of equipment, such as between a satellite and a ground station. Various data formats and protocols have evolved to facilitate communication in differing situations. Communication may involve multiple access technologies such as CDMA (code division multiple access), TDMA (time division multiple access), FDMA (frequency division multiple access), modulation technologies such as PSK (phase shift keying), QAM (quadrature amplitude modulation), and FEC (forward error correction) such as Reed Solomon coding, convolutional encoding, and turbo coding, by way of example.
In high-speed communication systems, digital circuitry, particularly with digital programmable devices, is employed advantageously for processing the signals in high-speed communication systems. Digital circuitry (application specific integrated circuits (ASICs)) has been capable of achieving the required speed. Currently, the industry is a pursuing the use of programmable digital devices, which have not been able to achieve the desired speeds with currently available technology. Accordingly, there is concern that the digital circuitry should be able to function with sufficient speed to handle the high data rates associated with high-speed communication systems.
Industry today, for both commercial and military applications, is requiring modem hardware that is reconfigurable (programmable) by use of software. By way of example, it would be desirable that a telephone operating in the United States would have the capability to operate in Europe upon a reconfiguration of the software. The technology is known in the industry as software-defined radios, and requires that the hardware be programmable. Digital programmable signal-processing devices such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs) are employed in the programmable wireless communications technology. These devices provide great flexibility and programmability, but their use, in the prior art, is at the expense of reduced processing speed, as compared to an ASIC by way of example.
To attain increased hardware flexibility, it is necessary to increase the rate of signal processing. By way of example, an increased rate of signal processing would allow for the transmission and the reception of multiple frequency channels, as in a frequency-division multiplex system, and would allow for digital frequency hopping in frequency-hopping spread spectrum systems, thereby eliminating the need for expensive and bulky synthesizers. A higher signal-processing rates allow for increased signal-transmission rates. It is noted that presently available A/D (analog-to-digital) and D/A (digital-to-analog) converters can operate at rates higher than 1000 million samples per second. In contrast, presently available digital signal processing is accomplished at a much slower rate in a digital signal-processing device such as the FPGA. The most common digital signal processing operation is FIR (finite impulse response) filtering, which appears in modulators and demodulators in the form of various processing functions such as decimation, interpolation, pulse shaping, matched filtering, and equalization, by way of example. Known realizations (implementations) of FIR filters result in filters operable only at reduced signal-processing speed when constructed in FPGAs and DSPs due to the speed limitations of these devices.
Generally, in a communication system, incoming signals are received by a demodulation section of a modem, while outgoing signals are transmitted by a modulation section of the modem. By way of example in the construction of a demodulation section of a modem employing digital signal processing, an analog-to-digital converter is employed to convert the incoming analog signal to a digitally formatted signal prior to the implementation of the digital signal processing. The digital signal processing involves various forms of filtering, by way of example, and is accomplished generally by use of computational type circuitry such as FPGAs and DSPs. It is well known that circuitry employed for conversion from analog signal format to digital signal format is able to operate at a sample rate which is significantly faster than the rate for computational circuitry such as the FPGAs and the DSPs. Therefore, at the present time, the limitation on the digital processing speed of a communication channel is the nature of the construction of a digital filter that has been implemented by an FPGA or a DSP. While an application-specific integrated circuit (ASIC) may be employed to accomplish a filter function at a higher sample rate than an FPGA or a DSP, the ASIC is designed for a specific signal format or modulation, while the FPGA or the DSP have the advantage of being programmable to be adapted readily for a variety of signal formats and modulations. Thus, the digital signal processing circuitry presently available in FPGAs and DSPs introduce a disadvantageous limitation on the maximum sample rate for digital signal processing, such as the filtering of a signal, in a modulation or a demodulation section of a modem.